Machine code detective

A 32-bit instruction word arrives on standard input in hex. If it is an add or subtract between registers (the shifted-register format), take it apart and print the instruction it encodes. With the stdin box as given the program prints:

sf=1 op=0 S=0 shift=0 imm6=0
Rm=2 Rn=1 Rd=0
add x0, x1, x2

The format, from bit 31 down:

• sf is 1 for x registers and 0 for w registers
• op is 0 for add and 1 for sub; S is 1 when the instruction sets the flags, so op * 2 + S indexes the mnems table (add, adds, sub, subs)
• shift picks lsl, lsr or asr (3 is not allowed), and imm6 is how far Rm is shifted first; leave the shift off the printed line when imm6 is 0
• in this format register number 31 is the zero register, printed xzrzero register (xzr / wzr): reads as zero, writes are discarded. or wzrzero register (xzr / wzr): reads as zero, writes are discarded.

ubfx wD, wN, lsb, width copies width bits starting at bit lsb into the bottom of wD, which is exactly what each field needs. A word whose bits 28 to 24 are not 01011, whose bit 21 is 1, or whose shift field is 3 is some other instruction: print not an add or sub (shifted register) and return 1.

What is checked

• all three lines for the word in the stdin box, and for more words you cannot see
• the exit status (0, or 1 for a word of another format)
• the fields come out with ubfxUnsigned bitfield extract: Rd = (Rn >> lsb) & ((1 << width) - 1).