Carry chains for extended-precision values (wider than one register), the shift-and-add multiplication algorithm, and the flag rules behind signed comparison.
0 of 5 correct
Multiple choice
A 192-bit value is held in three 64-bit registers. Two such values are added low word first. Which instruction sequence is correct for the low, middle, and high words?
Multiple choice
Which sequence is the subtraction counterpart of adds, adcs, adc for extended-precision arithmetic?
Multiple choice
In the shift-and-add multiplication algorithm for M * N, when is the multiplicand M added to the accumulator T?
Multiple choice
Multiplying two 64-bit values can produce a result that does not fit in one register. How is the full product held?
Multiple choice
Why can the signed lt condition not be decided by testing the Negative (N) flag alone?